1. Technical Field
The present invention relates to the electrical testing of so-called RF integrated circuits comprising inputs and outputs designed to receive or deliver AC signals in the radio frequency (RF) domain.
The present invention more particularly relates to the electrical testing of RF integrated circuits present on a silicon wafer before the wafer is sliced into individual components.
2. Description of the Related Art
By way of an example, FIG. 1 shows a silicon wafer 1 on which a large number of integrated circuits 2 having the same structure have-been made by photolithography. The magnified view of FIG. 2 shows an integrated circuit 2 with an active zone 3 and connection pads 4 electrically connected to the active zone 3. A greater magnification of the active zone 3 would reveal hundreds or even thousands of integrated circuits together forming various electronic functions that have to be tested.
Since the manufacturing yields for integrated circuits are below 100%, the electrical testing of the integrated circuits 2 that are still on the wafer 1 makes it possible to identify and reject defective integrated circuits or circuits lacking the expected characteristics, before the slicing of the wafer and the mounting of the individualized integrated circuits in a package or on an interconnection medium. This operation is therefore essential for reducing production costs, especially in the context of mass production.
FIG. 3 gives a schematic view of a conventional system for the testing of integrated circuits and wafers, comprising a test station 11 connected to a probe 12 by means of a harness of electrical cables 13. The probe 12 is a printed circuit card 14 provided with metal tips 15 arranged to coincide. with the connection pads; of an integrated circuit 2. The wafer 1 is positioned on a tray 16 that is mobile in the horizontal plane and the integrated circuits are tested one after the other by shift motions and rising and descending motions of the tray 16. The entire system is steered by a test program loaded into a memory 17 that determines the electrical characteristics of the test signal to be applied to the integrated circuits and the measurements to be made.
This conventional procedure for the testing of integrated circuits by means of a probe tip card, which is in widespread use in the industry, is nevertheless limited when it is sought to test RF integrated circuits comprising RF inputs/outputs requiring measurement frequencies ranging from some hundreds of MegaHertz to some GigaHertz. These are special integrated circuits having analog modulation and demodulation functions, mixers, amplifiers, filters, voltage-controlled oscillators (VCOs), phase-locked loops (PLLs), etc. designed for radio receivers, television receivers, mobile radiotelephones, GPS receivers, etc. In this frequency domain, the electrical signals have short wavelengths and various phenomena of reflection and phase rotation appear in the probe 12 and in the conductors 13 connecting the probe to the test station 11. These phenomena of reflection and rotation distort the electrical measurements by creating interference and changes of electrical level. Furthermore, at high frequency, the copper tracks of the printed circuit card 14 and the probe tips 15 of the probe 12 have non-negligible parasitic capacitance and inductance.
To overcome these drawbacks, specialized firms have developed RF probes offering satisfactory characteristics at high frequency. In particular, the firm Cascade Microtech in Oregon, 97005 USA, proposes RF probe tips (xe2x80x9ctransmission line probesxe2x80x9d) referenced xe2x80x9cAir Coplanarxe2x80x9d and RFIC membrane probe cards provided with microstrip HF conductors and contact bumps made of nickel. Probes of this kind offer a passband of several tens of Gigahertz, a low reflection coefficient S11 and a transmission coefficient S12 with an attenuation of less than 3 dB (see presentation of Cascade(trademark) products on http//www.cmicro.com).
At the same time, the manufacturers of measuring instruments such as the firm Teradyne(trademark) have developed test stations (the A580 series) having RF ports fitted out with an integrated network analyzer or vector network analyzer capable of determining the xe2x80x9cISxe2x80x9d parameters (S11, S12/S21 and S22) of a probe by the OSL (open, short, load) method. As is well known to those skilled in the art, the OSL method consists of the performance of three measurements by the successive application, to the output of the probe, of at least three standard loads, generally an infinite impedance (open circuit), a zero impedance (short circuit) and a 50 ohm impedance (load). On the basis of these three measurements, which are kept in the memory of the instrument, the vector network analyzer determines the xe2x80x9cSxe2x80x9d parameters of the probe, and the test station, during subsequent measurements, makes an automatic error correction designed to compensate for the influence of these parameters to obtain precise and reliable measurements. At present, the standard loads used are thin-layer circuits on ceramic substrate, calibrated by a national metrology laboratory.
These various means for the electrical testing of RF integrated circuits do not enable the implementation of a satisfactory xe2x80x9con-linexe2x80x9d testing method.
Firstly, the Air Copyanar type RF transmission line probes require a manual setting of the orientation of tips and are reserved for laboratory measurements or small production outputs. The membrane probe cards provided with contact bumps, although specially designed for the testing of integrated circuits on wafers, require the use of standard circuits with specific high-cost thin layers in order to be calibrated. For various other practical reasons, the membrane probe cards are not appropriate for the mass production of integrated circuits where the numbers of units manufactured could amount to several millions.
Secondly, at each calibration, the tips or contact bumps of the probes are applied forcefully to the connection pads of the standard circuits, so as to break a surface layer of oxide that forms in contact with air and set up a good electrical contact (xe2x80x9ccold weldingxe2x80x9d). The thin-layer standard circuits, apart from their high cost price, are therefore subject to wear and tear and have short lifetimes.
Finally, the thin-layer standard circuits do not have the same thickness as silicon wafers and, in order to be installed, require an adjustment of the tray 16 (FIG. 3) which is necessarily followed by another adjustment of the tray when the wafer is installed. This drawback is in addition to the fact that the RF probes require-several calibration operations during the testing of a batchof chips. These various calibrations imply action by a qualified engineer and take up 5 to 10% of the time devoted to electrical testing.
Thus, a general goal of the present invention is to provide for a method for the calibration of an RF probe that is suited to mass production, and is economical and easy to implement while at the same time being precise and reliable and capable of being implemented, if necessary, by non-skilled staff.
A more particular goal of the present invention is to provide for a standard circuit that has a low cost price and simplifies the calibration of an RF integrated circuit probe.
These goals are achieved by providing for a method for the calibration of an RF integrated circuit probe comprising a step for the determining, by means of a vector network analyzer and standard circuits, of the characteristics of the RF transmission lines of the probe, wherein the determining step is achieved by means of standard circuits present on a silicon wafer, said standard circuits comprising contact pads corresponding in their layout to RF connection pads of the integrated circuit to be tested and being differentiated from each other by different characteristic impedances measurable from their contact pads.
According to one embodiment, the method comprises a preliminary step for the measurement of the values of the characteristic impedances of said standard circuits, carried out by means of a measurement device previously calibrated by means of reference loads calibrated by a certified laboratory.
The values of the characteristic impedances of said standard circuits may be given to the vector network analyzer by means of a data recording medium. They can also be read in remranent type memories that are laid out in said standard circuits and are read-accessible or write-accessible through contact pads of said standard circuits which correspond to non-RF connection pads of the integrated circuit to be tested.
Preferably, the calibration of the probe is done by means of a first standard circuit comprising contact pads not connected to each other, a second standard comprising short-circuited contact pads and a third standard circuit comprising contact pads connected by electrical resistors.
The calibration of the probe can furthermore be verified by means of at least one fourth standard circuit comprising contact pads connected by capacitors and inductors.
According to the invention, the silicon wafer has only standard circuits or it comprises RF integrated circuits to be tested and standard circuits instead of certain RF integrated circuits.
According to one embodiment, said standard circuits comprise elementary standard structures comprising at least two contact pads deposited on an electrically insulating layer, a conductive screen buried beneath the insulating layer and contact pads overhanging the conductive screen.
The elementary standard structures may include two series-mounted standard loads connected by their midpoint to the conductive screen and at least one virtual ground pad for the measurement of the impedance values of each standard load.
The present invention also relates to a method for the electrical testing of an RF integrated circuit present on a silicon wafer, comprising a step for the calibration of the probe according to the above-described method, wherein the RF characteristics of the probe are used as corrective terms during the electrical testing of the integrated circuit.
According to one embodiment, the probe comprises a printed circuit card provided with short contact probe tips. The RF transmission lines of the probe may include capacitors and coils to compensate at least partly for the influence of parasitic capacitances and inductances.